1. Field of the Invention
The present invention relates to a synchronizing circuit for synchronizing a digital input signal and a clock signal, said circuit including a detection circuit to detect the presence/absence of synchronism between said input signal and said clock signal and to accordingly provide a phase adjustment signal indicative of said presence/absence of synchronism and a phase adjustment circuit controlled by said phase adjustment signal to perform a relative phase shift between said input signal and said clock signal when absence of synchronism is detected and providing an output signal synchronized with said clock signal.
2. Description of the Prior Art
Such a synchronizing circuit is already known in the art, e.g. from the International Patent Application PCT/EP88/00272. In this known synchronizing circuit the detection circuit detects the presence/absence of synchronism between the digital input signal and the clock signal by interpreting the relationship between at least two samples of a regenerated output signal which is obtained by passing the input signal through the phase adjustment circuit comprising a variable delay circuit covering one period of the input signal. This phase adjustment circuit, under the control of the phase adjustment signal generated by the detection circuit, performs a relative phase shift between the regenerated output data signal and the clock signal by adapting the above mentioned variable delay value.
A first drawback of this known synchronizing circuit is that the detection circuit operates directly on the input signal since it successively subjects this input signal to different delays, in a stepwise manner and under control of the phase adjustment signal, to reach synchronism. This means that the time to reach synchronism may be relatively high when many successive delays are necessary, which is another drawback of the existing synchronizing circuit.
Still another drawback is that the samples of the regenerated output have to be taken within half of the period of the input signal and at a very small time interval which implies a complex and accurate delay circuit. Such a delay circuit may be relatively expensive, especially when the synchronizing circuit has to operate at high frequency thus requiring technologies like gallium arsenide.